**兩隻小豬**

1. What is UVM factory?

UVM Factory is used to manufacture (create) UVM objects and components. Apart from creating the UVM objects and components the factory concept essentially means that you can modify or substitute the nature of the components created by the factory without making changes to the testbench.

UVM Factory 用於製造（創建）UVM 對象和組件。 除了創建 UVM 對象和組件之外，工廠概念本質上意味著您可以修改或替換工廠創建的組件的性質，而無需更改測試台。

For example, if you have written two driver classes, and the environment uses only one of them. By registering both the drivers with the factory, you can ask the factory to substitute the existing driver in the environment with the other type. The code needed to achieve this is minimal and can be written in the test.

例如，如果您編寫了兩個驅動程序類，而環境只使用其中一個。 通過向工廠註冊這兩個驅動程序，您可以要求工廠將環境中現有的驅動程序替換為另一種類型。 實現這一點所需的代碼很少，可以在測試中編寫。

2. What is the difference between new() and create?

We all know about new() method that is used to allocate memory to an object instance. In UVM (and OVM), the create() method causes an object instance to be created from the factory. This allows you to use factory overrides to replace the desired object with an object of a different type without having to recode.

我們都知道用於為對象實例分配內存的 new() 方法。 在 UVM（和 OVM）中，create() 方法導致從工廠創建對象實例。 這允許您使用工廠覆蓋將所需對象替換為不同類型的對象，而無需重新編碼。

3. What is uvm_config_db ? What is difference between uvm_config_db & uvm_resource_db?

uvm_config_db is a parameterized class used for configuration of the different type of parameter into the uvm database So that it can be used by any component in the lower level of a hierarchy.

uvm_config_db 是一個參數化類，用於將不同類型的參數配置到 uvm 數據庫中，因此它可以被層次結構中較低級別的任何組件使用。

uvm_config_db is a convenience layer built on top of uvm_resource_db, but that convenience is very important. In particular, uvm_resource_db uses a "last write wins" approach. The uvm_config_db, on the other hand, looks at where things are in the hierarchy up through end_of_elaboration, so "parent wins." Once you start start_of_simulation, the config_db becomes "the last write wins."

uvm_config_db 是建立在 uvm_resource_db 之上的便利層，但便利性非常重要。 特別是，uvm_resource_db 使用“最後一次寫入獲勝”的方法。 另一方面，uvm_config_db 通過 end_of_elaboration 查看事物在層次結構中的位置，因此“parent wins.”。 一旦你啟動 start_of_simulation，config_db 就變成了“最後寫入獲勝”。

All of the functions in uvm_config_db#(T) are static, so they must be called using the:: operator

It is extended from the uvm_resource_db#(T), so it is a child class of uvm_resource_db#(T)

uvm_config_db#(T) 中的所有函數都是靜態的，因此必須使用:: 運算符調用它們

它是從 uvm_resource_db#(T) 擴展而來的，所以它是 uvm_resource_db#(T) 的子類

4. What is the advantage and difference of  `uvm_component_utils() and `uvm_object_utils()?

The utils macros define the infrastructure needed to enable the object/component for correct factory operation.

utils macros 定義了啟用對象/組件以進行正確的工廠操作所需的基礎結構。

The reason there are two macros is that the factory design pattern fixes the number of arguments that a constructor can have. Classes derived from uvm_object have constructors with one argument, a string name. Classes derived from uvm_component have two arguments, a name, and a uvm_component parent.

有兩個macros的原因是工廠設計模式固定了構造函數可以擁有的參數數量。 從 uvm_object 派生的類具有帶有一個參數的構造函數，即字符串名稱。 從 uvm_component 派生的類有兩個參數，一個名稱和一個 uvm_component 父級。

The two `uvm_*utils macros insert code that gives you a factory create a () method that delegates call to the constructors of uvm_object or uvm_component. You need to use the respective macro so that the correct constructor arguments get passed through. This means that you cannot add extra constructor arguments when you extend these classes in order to be able to use the UVM factory.

兩個 `uvm_*utils macros插入代碼，為您提供工廠創建 () 方法，該方法將調用委託給 uvm_object 或 uvm_component 的構造函數。 您需要使用相應的macros，以便傳遞正確的構造函數參數。 這意味著當您擴展這些類以便能夠使用 UVM 工廠時，您不能添加額外的構造函數參數。

5. Difference between `uvm_do and `uvm_rand_send ?

`uvm_do perform the below steps:

1. create

2. start_item

3. randomize

4. finish_item

5. get_response (optional)

while `uvm_rand_send perform all the above steps except create. User needs to create sequence / sequence_item.

而 `uvm_rand_send 執行除創建之外的所有上述步驟。 用戶需要創建sequence/sequence_item。

6. Difference between uvm_transaction and uvm_seq_item?

class uvm_sequence_item extends uvm_transaction

uvm_sequence_item 類擴展了 uvm_transaction

uvm_sequence_item extended from uvm_transaction only, uvm_sequence_item class has more functionality to support sequence & sequencer features. uvm_sequence_item provides the hooks for sequencer and sequence So you can generate transaction by using sequence and sequencer, and uvm_transaction provide only basic methods like do_print and do_record etc.

uvm_sequence_item 僅從 uvm_transaction 擴展而來，uvm_sequence_item 類具有更多功能來支持序列和序列器功能。 uvm_sequence_item 提供了sequencer 和sequence 的鉤子，所以你可以使用sequence 和sequencer 生成事務，而uvm_transaction 只提供do_print 和do_record 等基本方法。

7. Can we have a user-defined phase in UVM?

In addition to the predefined phases available in uvm, the user has the option to add his own phase to a component. This is typically done by extending the uvm_phase class the constructor needs to call super.new which has three arguments

除了 uvm 中可用的預定義階段外，用戶還可以選擇將自己的階段添加到組件中。 這通常通過擴展構造函數需要調用 super.new 的 uvm_phase 類來完成，該類具有三個參數

Name of the phase task or function

Top down or bottom up phase

Task or function

The call_task  or call_func and get_type_name need to be implemented to complete the addition of the new phase.

需要實現 call_task 或 call_func 和 get_type_name 才能完成新階段的添加。 

8. What is UVM RAL model? why it is required?

In a verification context, a register model (or register abstraction layer) is a set of classes that model the memory mapped behavior of registers and memories in the DUT in order to facilitate stimulus generation and functional checking (and optionally some aspects of functional coverage). The UVM provides a set of base classes that can be extended to implement comprehensive register modeling capabilities.

 在驗證上下文中，寄存器模型（或寄存器抽象層）是一組類，它們對 DUT 中寄存器和存儲器的存儲器映射行為進行建模，以促進激勵生成和功能檢查（以及可選的功能的某些方面） 覆蓋）。 UVM 提供了一組基類，可以對其進行擴展以實現全面的寄存器建模功能。

10. What is the analysis port?

Analysis port (class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be connected to zero, one, or many analysis exports and through which a component may call the method to write implemented in another component, specifically a subscriber.

port, export, and imp classes used for transaction analysis.

分析端口（類 uvm_tlm_analysis_port）— 一種特定類型的事務級端口，可以連接到零個、一個或多個分析導出，並且組件可以通過該端口調用在另一個組件中實現的方法，特別是訂閱者。

uvm_analysis_port

Broadcasts a value to all subscribers implementing a uvm_analysis_imp.

向所有實現 uvm_analysis_imp 的訂閱者廣播一個值。

uvm_analysis_imp

Receives all transactions broadcasted by a uvm_analysis_port.

接收 uvm_analysis_port 廣播的所有交易。

uvm_analysis_export

Exports a lower-level uvm_analysis_imp to its parent.

將較低級別的 uvm_analysis_imp 導出到其父級。

11. What is TLM FIFO?

In simpler words, TLM FIFO is a FIFO between two UVM components, preferably between Monitor and Scoreboard. Monitor keep on sending the DATA, which will be stored in TLM FIFO, and Scoreboard can get data from TLM FIFO whenever needed.

簡單來說，TLM FIFO 是兩個 UVM 組件之間的 FIFO，最好在 Monitor 和 Scoreboard 之間。 Monitor 不斷發送 DATA，DATA 將存儲在 TLM FIFO 中，Scoreboard 可以在需要時從 TLM FIFO 中獲取數據。

12. How the sequence starts?

start_item starts the sequence

start_item and finish_item together will initiate operation of a sequence item.  If the item has not already been initialized using create_item, then it will be initialized here to use the default sequencer specified by m_sequencer.

start_item 和 finish_item 一起將啟動序列項的操作。 如果該項目尚未使用 create_item 進行初始化，則將在此處對其進行初始化以使用 m_sequencer 指定的默認排序器。

13. What is the difference between UVM RAL model backdoor write/read and front door write/read?

Front door access means using the standard access mechanism external to the DUT to read or write to a register. This usually involves sequences of time-consuming transactions on a bus interface.

前門訪問意味著使用 DUT 外部的標準訪問機制來讀取或寫入寄存器。 這通常涉及總線接口上的一系列耗時事務。

Backdoor access means accessing a register directly via hierarchical reference or outside the language via the PLI. A backdoor reference usually in 0 simulation time.

後門訪問意味著通過分層引用直接訪問寄存器或通過 PLI 在語言之外訪問。 後門引用通常在 0 仿真時間。

14. What is the objection?

The objection mechanism in UVM is to allow hierarchical status communication among components which is helpful in deciding the end of the test.

UVM 中的反對機制是允許組件之間的分層狀態通信，這有助於決定測試的結束。

There is a built-in objection for each in-built phase, which provides a way for components and objects to synchronize their testing activity and indicate when it is safe to end the phase and, ultimately, the test end.

每個內置階段都有一個內置反對，它為組件和對象提供了一種同步其測試活動的方法，並指示何時可以安全地結束該階段並最終結束測試。

The component or sequence will raise a phase objection at the beginning of an activity that must be completed before the phase stops, so the objection will be dropped at the end of that activity. Once all of the raised objections are dropped, the phase terminates.

組件或序列將在必須在階段停止之前完成的活動開始時提出階段異議，因此該異議將在該活動結束時被刪除。 一旦所有提出的反對意見都被放棄，該階段就結束了。

Raising an objection: phase.raise_objection(this);

Dropping an objection: phase.drop_objection(this);

15. What is p_sequencer ? OR Difference between m_sequencer and p_sequencer?

m_sequencer is the default handler for uvm_vitual_sequencer and p_sequencer is the hook up for child sequencer.

m_sequencer 是 uvm_vitual_sequencer 的默認處理程序，而 p_sequencer 是子序列器的掛鉤。

m_sequencer is the generic uvm_sequencer pointer. It will always exist for the uvm_sequence and is initialized when the sequence is started.

m_sequencer 是 uvm_vitual_sequencer 的默認處理程序，而 p_sequencer 是子序列器的掛鉤。

p_sequencer is a type-specific sequencer pointer, created by registering the sequence to the sequencer using macros (`uvm_declare_p_sequencer). Being type specific, you will be able to access anything added to the sequencer (i.e. pointers to other sequencers, etc.). p_sequencer will not exist if we have not registered the sequence with the `uvm_declare_p_sequencer macros.

p_sequencer 是一個特定類型的序列器指針，通過使用macros (`uvm_declare_p_sequencer) 將序列註冊到序列器來創建。 由於類型特定，您將能夠訪問添加到音序器的任何內容（即指向其他音序器的指針等）。 如果我們沒有使用 `uvm_declare_p_sequencer macros註冊序列，p_sequencer 將不存在。

The drawback of p_sequencer is that once the p_sequencer is defined, one cannot run the sequence on any other sequencer type.

p_sequencer 的缺點是一旦定義了 p_sequencer，就不能在任何其他類型的定序器上運行序列。

16. What is the difference between Active mode and Passive mode with respect to the agent?

An agent is a collection of a sequencer, a driver and a monitor.

代理是定序器、驅動程序和監視器的集合。

In active mode, the sequencer and the driver are constructed and stimulus is generated by sequences sending sequence items to the driver through the sequencer. At the same time, the monitor assembles pin level activity into analysis transactions.

在主動模式下，將構建定序器和驅動器，並通過序列通過定序器將序列項發送到驅動器來生成激勵。 同時，監視器將引腳級別的活動組裝到分析事務中。

In passive mode, only the monitor is constructed and it performs the same function as in an active agent. Therefore, your passive agent has no need for a sequencer. You can set up the monitor using a configuration object.

在被動模式下，僅構建監視器並執行與主動代理相同的功能。 因此，您的被動代理不需要定序器。 您可以使用配置對象設置監視器。

17. What are the types of sequencer? Explain each?

There are two types of sequencer:

uvm_sequencer #(REQ, RSP) :

When the driver initiates new requests for sequences, the sequencer selects a sequence from a list of available sequences to produce and deliver the next item to execute. In order to do this, this type of sequencer is usually connected to a driver uvm_driver #(REQ, RSP).

當驅動程序發起對序列的新請求時，定序器從可用序列列表中選擇一個序列來生成並交付下一個要執行的項目。 為了做到這一點，這種類型的定序器通常連接到驅動程序 uvm_driver #(REQ, RSP)。

uvm_push_sequencer #(REQ, RSP) :

The sequencer pushes new sequence items to the driver, but the driver has the ability to block the item flow when it's not ready to accept any new transactions. This type of sequencer is connected to a driver of type uvm_push_driver #(REQ, RSP).

排序器將新的序列項推送給驅動程序，但驅動程序有能力在它還沒有準備好接受任何新事務時阻止項目流。 這種類型的定序器連接到 uvm_push_driver #(REQ, RSP) 類型的驅動程序。